Insight on the Future Trends in Automated Test Equipment


For the years to come, analysts expect significant growth in the global automated test equipment (ATE) market, driven by the introduction of new technologies, highly integrated electronic components and by the greater complexity of new electronic devices. The reduced time-to-market, combined with the need to provide high quality standards for even the most advanced functionalities, are pushing manufacturers towards automatic test solutions, whose reliability and repeatability guarantees a significant reduction in time, maintenance and costs. ATEs help manufacturers to perform accurate tests and measurements, reducing the incidence of failures and errors, and providing test results much faster than with manual testing methodology. In view of growing competition and the consequent need to achieve economies of scale providing high quality products able to meet the growing consumer demand, manufacturers around the world are adopting automated testing techniques. The ATE solution in vertical sectors, such as semiconductor, consumer, automotive, industrial, aerospace and defense is set to grow the best in the coming years.

ATE classes

Automated Test Equipment (ATE) is a computer-controlled system that allows the automatic test of components, printed circuit boards, interconnections or entire electronic devices with minimal operator intervention. The advantages offered by an ATE include reduced test times, repeatability of the verification procedure and cost savings, especially in the case of high DUT (Device Under Test) volumes.

A first type of ATE deals with performing the test of semiconductors and integrated circuits. By applying a predetermined and programmable pattern of electrical signals to a semiconductor or an IC, the ATE measures the corresponding output signals and compares them with expected values or ranges. These systems can in turn be divided into logic testers, memory testers, and analog testers. Semiconductor testing, with DUTs ranging from common silicon-based components to complex integrated circuits and System-On-Chip (SoC), is normally divided into two levels. The first is the wafer test (also called die sort or probe test), whose task is to test the wafers. The second is the package test (also called final test), performed on the component after packaging. The wafer test uses a prober and a probe card, while the test package uses a handler and a test socket. The DUT is physically connected to the ATE through a device called handler, or prober, and through a customized Interface Test Adapter (ITA) that adapts the ATE resources to the DUT. This class of ATE includes logic test systems, designed to test microprocessors, FPGAs, ASICs and other logic devices, linear or mixed signal equipment (for testing ADCs, DACs, amplifiers, comparators and video devices), passives components ATEs (capacitor, resistor, inductor) and discrete ATEs (MOSFET, SCR, Zener, JFET, etc.).

ElevATE Semiconductor, a leading supplier of innovative, low power, high density components for the design of next generation Automated Test Equipment (ATE), provides Mystery (visible in Figure 1), a 500 MHz SoC with eight independent pin channels for ATE equipment. Each channel is configured via a 50MHz SPI interface, and all real time data is programmed and read back through high speed FLEX I/O pins that can be configured to interface directly to other devices using multiple single-ended and differential logic families.

Figure 1: ElevATE Mystery SoC

New Rainier SOC 8 Channel / 1.6GHz

This new pin electronics SoC increases speed by 50%, reducing power by 67% and total size by 75%. A 50% speed increase allow to test even the most performant processor, SoC, FPGA, and memory technologies. A 67% power reduction allows to triple the number of pins or DUTs without increasing the power budget. A 75% size reduction allows to quadruple the number of pins under test without expanding the overall PCB size.

The second type of ATE deals with PCB testing (both before wave soldering and after assembly) in order to detect any manufacturing errors and ensuring that each product leaves the factory free from defects. Automated PCB testing includes optical inspection techniques, such as Automatic Optical Inspection (AOI) and Automatic X-Ray Inspection (AXI), flying probe test, and bed-of-nails in-circuit fixture test.

Finally, the interconnection testing verifies the status and quality of interconnections, cables and connectors. In particular, it is able to detect opens (missing connections), shorts (open connections) and miswires (wrong pins) on cable harnesses, distribution panels, flexible circuits, and membrane switch panels with commonly used connector configurations. Interconnection testing also includes resistance and hipot tests.

For Test During Burn-In (TDBI) applications and low-cost testers, ElevATE offers the Kilimanjaro SoC, shown in Figure 2. Fabricated in a wide voltage Bi-CMOS process, the Kilimanjaro incorporates two channels of programmable drivers and window comparators into a small 5mm x 5mm QFN package. Each channel has per pin driver levels, data, and high impedance control, along with per-pin high and low window comparator thresholds levels.

Figure 2: ElevATE Kilimanjaro SoC

ATE market segmentation

ATE market can be segmented based on the type of product, application or geographical area. Regarding the product, the market is divided into non-memory, memory, and discrete automated test equipment. Recent innovations in sectors such as IoT and automotive (including autonomous vehicles), together with the significant advances made by defense and aerospace sectors, are changing the dynamics of the market. The main objective of manufacturers is to improve customer satisfaction by providing superior quality and reducing both time-to-market and testing costs. Based on the application, main ATE market categories include automotive, consumer, aerospace and defense, telecommunications and medical. Geographically, the global ATE market is dominated by North America, whose market share is expected to grow further in the coming years, as well. The main drivers of growth are determined by the increasing application of ATEs in the aerospace and defense sectors. The global markets of Europe and Asia-Pacific are also expected to grow, with a CAGR between 3% and 4% through the 2020-2022 time horizon. In the same forecast period, the Asia-Pacific market is expected to become the largest regional segment, due to the significant presence of semiconductor industries.

Market future prospects

The global ATE market size, valued at over four U.S. billion dollars in 2019, is expected to witness an important growth over the next few years. According to analysts, this growth will be driven by the increasingly widespread use of ATEs in the automotive and semiconductor industry, the adoption of 5G technology, and Artificial Intelligence/IoT markets growing rapidly. Other key factors are the significant increase in the number of connected devices and consumer electronics, with the need to provide high quality products reducing the time to market. The growing adoption of highly integrated electronic components, such as System on Chip (SoC) and FPGAs, and the high demand for consumer electronics will be a driving force for the growth of the ATE market in the coming years. Moreover, the miniaturization and complexity of the latest generation electronic components will broaden the areas of application of ATEs.

The tremendous progress made in semiconductor manufacturing processes, coupled with the expansion of connected devices in developing countries and the spread of the IoT network, will be a driving force for the growth of the automated test equipment market in the coming years. Furthermore, the considerable technological advances associated with the complexity of the design and the need for effective test systems are factors that will favor the expansion of the ATE market. The latest electronic technologies have significantly reduced the costs and time required for manufacturing integrated circuits and semiconductors, increasing the profit margin reserved for companies. This represents an important opportunity for ATE manufacturing companies, whose priority is to constantly invest in research and development in order to improve their product portfolio by adapting to the latest trends in the electronics sector.

Supply Chain 2021

Look back on 2020, I want to thank our customers and supply partners for a great year, despite all the global challenges.

As we look forward, there is a consensus across the industry that we all are entering a period of significant expansion in the semiconductor market.  Across almost all market verticals, strong growth is forecasted for the next several years.  And like all semiconductor manufacturers, we are seeing some impacts show up in our supply chain.  Capacity has tightened, and lead times are extending across the industry.

With this constrained supply environment, we are asking our customers to please increase the frequency, time horizon, and the accuracy of your forecasts where possible.  Current product lead times have extended to 7 months on average.  We continue to procure supply to our customers forecasts.  We will always strive to meet all our customers demand, however unforecasted demand may prove to be challenging.

For the highest level of support, we ask customers to forecast their demand monthly, with a 12 month time horizon, and to place orders with 8 to 12 weeks of leadtime.  Unforecasted demand, and orders inside 8 weeks are subject to a 15% cost adder to mitigate the expedite fees we are charged by our supply partners.

Thank you for your continued support, and the privilege of being your ATE technology partner

Adam Haigis, Vice President of Operations

David Kenyon: Looking Forward to 2021

Hello and Happy 2021!  I hope this note finds you healthy and ready for the New Year.  We @ Elevate have been very busy at the end of 2020, and we see the pace quickening into ’21.  As you may have read in other posts, the semiconductor supply chain is getting crowded and filling up – orders are booking out longer and longer and we are working our supply chain magic to refill shelves with inventory after a very busy year.  We also have new product – Mystery final silicon is shipping today, the Whitney production parts have shipped and are in house for testing, and we should complete another tapeout on our next gen pin electronics by the end of January (knock on wood!).  We’ve never had so much new product either in the fab, or in house for test at the same time! 

Our company is growing, too – we’re adding operations people, business/administration people, and of course, design engineers and product engineers. 

While we are proud that we came out of 2020 healthy and growing, we are sensitive to the needs of our customers and partners around the world and we can’t wait to re-engage in person this year, when conditions permit.  Video calls are a good tool, but nothing takes the place of sitting down with you and learning about your business, and your test needs.  I’m looking forward to being able to do that in 2021!

Have a great year, and please remember to get us your forecast early this year.. so we can make sure we have you covered for the demand surge that is hitting everyone these days. 



From Our CEO: Working With ElevATE

“As our industry continues to consolidate, we find that our customers are more interested today in creative ways to partner together to solve their test needs; requirements vary significantly from the recent past of simply using a one-size-fits all approach of buying off the shelf parts and spending lots of R&D on board design.  We are finding more unique ways to leverage one of the world’s largest portfolios of analog test IP in putting together semi-custom parts, derived from either something in our existing portfolio or using IP from multiple designs.  Since we are solely focused on this market, we are able to build these designs at lower cost and faster than large companies who have a main business far outside of ATE and test; our threshold of investment for custom and semi-custom applications can be a factor of 10X lower than multi-billion dollar public companies in this space.

Which, I would argue, is why there is only one public company left in test – this market is not a place for people who are not patient, take a long-term view, and are focused on the needs of test customers.. not Wall Street quarterly earnings reports.

When you have unique test requirements that fall outside the bounds of off-the-shelf ATE offerings, engage us and let us use our IP to find a solution that works for you, with an investment level you can manage.”

5G Test

Challenges involved in 5G Testing


The imminent large-scale rollout of 5G technology imposes new and tough challenges for designers of PCB, network equipment and electronic devices in general. 5G will not only represent an increase in data rates, but it will be a real revolution, with latency times reduced up to 1ms and the use of millimeter waves (mmWave) to support greater bandwidth. PCBs for 5G mobile and network devices must be able to simultaneously manage higher digital data rates and higher frequencies, pushing mixed signal design to its limit. 5G applications will also pose a variety of new challenges for the engineers developing automated test equipment (ATE). Compared to the current 4G mobile network, the rollout of 5G will force designers to rethink the layout of PCBs used in mobile devices, data transmission networks and IoT infrastructure. Ensuring signal integrity at every point on the board represents one of the most difficult challenges imposed by 5G testing. Due to the presence of mixed signals, it will be necessary to prevent EMI between the analog and digital sections of the board, verifying that the FCC EMC requirements are met.

Impact of 5G features on testing

Transition from 4G to 5G network will not only result in a substantial improvement in data transmission rates and greater bandwidth availability but will also introduce new features that are destined to radically change many aspects of our lives. 5G network aims to provide 10-20x faster data rates (up to 1 Gbps), an increase in traffic of up to 1000x and an increase of up to 10x in the number of connections per square kilometer. Latency will be very low, of the order of 1ms, about ten times lower than that obtainable with a 4G network. Low latency is essential for the implementation of applications with real-time behavior, such as virtual reality and augmented reality (VR/AR), machine-to-machine (M2M) communication systems and autonomous vehicle infrastructure sensors.

5G networks will operate on a much wider frequency range than was available with previous mobile technologies. Printed circuits intended for mobile devices and network equipment will have to simultaneously manage high speed digital signals and high frequency RF signals, pushing mixed signal design to its limits. While 4G network uses frequencies between 600 MHz and 5.925 GHz, 5G network will significantly expand its upper frequency limit, pushing itself into the millimeter wave (mmWave) band. Bandwidth per channel is also an important factor affecting the design and testing of 5G PCBs and devices. While in 4G network the bandwidth per channel was equal to 20 MHz (limited to 200 kHz in IoT devices), in the fifth generation mobile network we will have a bandwidth per channel equal to 100 MHz for frequencies below 6 GHz and 400 MHz for frequencies above 6 GHz.

PCBs designed for 5G applications will require analog and digital components capable of operating at very high frequencies and data rates, whose reliability and efficiency can only be guaranteed through effective thermal management. Temperature monitoring is therefore another relevant factor for assessing a correct behavior of the PCB or device.

5G device testing

The performance requirements imposed by 5G technology will create unprecedented challenges in the testing of integrated circuits, System-On-Chip (SoC), PCBs, mobile devices and network equipment. Most 5G NR (New Radio) installations will use the 3.5 GHz frequency and the 28 GHz to 29 GHz frequency range. Both of these frequency ranges are new to the cellular network and will require architectural changes and modifications to radio access techniques. The ability to achieve greater network capacity and higher transmission data rates will require the use of advanced technologies, such as massive MIMO (multiple-input/multiple-output) and beamforming.

While still in the early stages of deployment, 5G technology is gaining momentum, posing urgent questions about how and at what cost to test mmWave devices used in different RF front-end module architectures and networking equipment. In addition, mmWave signals essentially propagate in the line-of-sight direction and are more subject to atmospheric attenuation than sub-6 GHz bands, resulting in the need to perform accurate tests capable of covering all operational scenarios. Phased array antennas, required to support advanced features such as beamforming, will benefit from the small size to allow for multiple antenna elements on the same PCB. The main challenge will be to reduce parasitics between the antenna and the low noise amplifier (LNA) on the receiving side, and with the power amplifier on the transmitting side. The fulfillment of the requirements must also be tested on the antenna, also using OTA (Over-The-Air) techniques. The use of millimeter waves will create new challenges for test systems. First of all, it will be necessary to reduce the distance that separates the test hardware and the cooling system from the probe environment, in order to minimize the particularly high-power losses created at mmWave frequencies. Additionally, testing boards and modules with integrated antenna will require a different approach, bearing in mind that in some cases only over-the-air communication between the test system and the DUT will be possible.

ATE tools

The complexity of the required compliance testing is growing exponentially with each new generation of mobile technology. Release 14 of 3GPP (which already contained some pre-5G functionality) specified about 15,000 tests, Release 15 (partial 5G) about 300,000 tests, whereas Release 16 (full 5G) will introduce additional tests. As the number of required tests goes up, the need for automated test systems increases, capable of supporting high frequencies and speeds and easily configurable. Automated Test Equipment (ATEs) are essential to ensure the proper functioning of PCBs, SoCs or individual components used in the implementation of the 5G network.

ElevATE Semiconductor is a leading company which provides world class test integrated circuits (ICs) that address the industry’s most complex ATE challenges. Designing state of the art chips, ElevATE delivers the highest density, lowest power ATE solutions available. ElevATE products can be grouped into four main categories, depending on the technology on which they are based:

  • integrated pin electronics products – ElevATE is the market leader in low power, high density integrated pin electronics. Developed in a pure CMOS technology, these products enable customers to develop next generation high density instruments with increased parallelism fro reduced cost and improved system reliability;
  • integrated DPS products – these Device Under Test (DUT) power supply solutions incorporate up to 8 independent DUT Power Supply Unit (DPS). The interface, the control, and the I/O are digital, while all analog circuitry is inside the chip. A single chip is able to provide a complete DPS solution;
  • integrated PMU/VI products – Parametric Measurement Units and Virtual Instruments provide best in class density as high as 8 channels per chip and voltage up to 60V. PMI and VI products are cost-sensitive solutions that provide both voltage and current source and measurement capability for a wide range of applications;
  • integrated high voltage products – based on a highly integrated dual channel wide voltage System-on-a-Chip (SoC) pin electronics solution, these products incorporate every analog function, along with some digital support functionality, required on a per channel basis for Automated Test Equipment.

Among ElevATE portfolio solutions is the Venus 4 (ISL55161), a highly integrated SoC incorporating a dual channel 400MHz/800Mbps pin electronics differential driver and comparator, active load, timing deskew, PMU and DAC. Available in a 64-Lead 10mm x 10mm TQFP and in a 64-Lead 9mmx9mm QFN package, the SoC features a Pdq ≤ 500mW/Channel @ 11V Operation.


Figure 1: Venus 4 (ISL55161)

The SoC, whose block diagram is shown in Figure 2, is particularly suitable for applications such as Automated Test Equipment (ATE), instrumentation and ASIC verifiers.

venus designs

Figure 2: Venus 4 block diagram


Using FPGA for Format and Timing Generation for Semiconductor ATE

ATE digital systems traditionally consist of sequencers, formatters, timing generators and pin electronics. The decision about which components to use for each section of the design is primarily driven by performance specifications and cost desired. These components range from discrete, fully custom ASIC, Field Programmable Gate Array or commercially available parts.

Field Programmable Gate Arrays (FPGA) provide flexibility and have been used for the sequencer and timing/formatting for low to medium performance ATE digital subsystems.

Implementing the sequencer with an FPGA provides flexibility to customize the digital subsystem for logic, memory or mixed signal test. The FPGA clocking required is typically well within the specifications of the target FPGA. The sequencer and pattern execution stages are typically what make each system unique compared to the competitors offering.

The format and timing functionality are typically similar amongst different ATE platforms. The differences are in the cycle to cycle edge placement resolution and accuracy as well as the fine skew control used for channel deskew calibration. The fine deskew control is often available in the pin electronics ICs.

FPGAs have been successfully used for the timing and format function, but the FPGA quickly becomes the limiting factor as the system performance requirements increase to above 50-100Mhz pattern rates and as the system edge placement accuracy is pushed below 1ns. While the SERDES engines in the FPGA I/O structures can provide <100ps resolution, implementing this reliability for edge to edge timing placement increases the design time and pushes the designer to choose larger and more expensive FPGA.

The most common usage of the SERDES blocks are for various communications protocols such as PCIe and the FPGA design tools provide excellent tools for designing and characterizing these functions. Designers often run into roadblocks when designing the timing section using these SERDES blocks and there are limited tools available from FPGA vendors to resolve issues. Designers often spend 10X the budgeted engineering hours implementing and characterizing these timing circuits. Typical issues include: inconsistent linearity from channel to channel, higher than acceptable jitter, and difficulty routing the design from run to run.

As designers attempt to increase the channel count they are required to migrate to larger and more expensive FPGAs. In the past, designers have been able to capitalize on faster and larger FPGAs at lower costs. In recent times, however, the focus of FPGA companies has been to increase compute capabilities to address the data center and artificial intelligence markets. This addition of more compute elements has increased the costs with minimal or negative benefits to the ATE designer. In addition, the costs of older devices that serve the ATE market have started going up dramatically especially for larger devices. This has pushed the cost for higher channel ATE using larger FPGAs up to $50/channel just for the FPGA.

To achieve higher performance ATE with pattern rates of 200+ MHz, ATE designers need to use custom or commercially available format and timing generator ICs. They are then able to use a reasonable cost FPGA for the sequencer portion of the design.

A commercially available timing generator would provide smaller ATE companies to migrate up the performance ladder in digital ATE instrumentation. These chips are designed to be interfaced to high performance pin drivers without requiring an over constrained FPGA I/O.

By purchasing timing chips with high end performance this would reduce the design, characterization and test times as well as reducing the cost per channel while offering higher performance digital ATE specifications. The timing accuracy is specified by the vendor and does not require extensive characterization and production testing of these parameters at system test.

Commercial timing chips will ultimately save an ATE company development cost and time to market as well as overall cost of the system, while providing a path to higher end performance.

MIPI5G 200

MIPI Specifications and Testing

The mobile industry processor interface (MIPI®) standard defines industry specifications for the design of mobile devices such as smartphones, tablets, laptops and hybrid devices. MIPI interfaces play a strategic role in 5G mobile devices, connected car and Internet of Things (IoT) solutions. The MIPI standard defines three unique physical (PHY) layer specifications: MIPI D-PHY®, M-PHY® and C-PHY®. MIPI D-PHY and C-PHY physical layers support camera and display applications, while the high-performance camera, memory and chip-to-chip applications are supported on top of the M-PHY layer.

MIPI is managed by MIPI Alliance which is a collaboration of mobile industry leaders which include Intel, Nokia, Samsung, Motorola, TI, ST etc.  The objective of MIPI Alliance is to promote open standards for interfaces to mobile application processors. This will help in having new services to mobile users at faster rate.

In the mobile market, MIPI Alliance specifications are targeted to mobile devices that operate on mobile networks. Typical devices are smartphones, tablets, laptops and hybrid devices. MIPI Alliance provides specifications that serve manufacturers’ various needs for physical layer, multimedia, chip-to-chip or interprocessor communications (IPC), control/data, debug/trace, and software integration applications.

All of the specifications are designed to address three characteristics essential to successful mobile designs:  1) low power to preserve battery life; 2) high-bandwidth to enable feature-rich, data-intensive applications, and 3) low electromagnetic interference (EMI) to minimize interference between radios and other subsystems in a device.


The smartphone industry is the largest single market for MIPI specifications. All major chip vendors use MIPI Alliance specifications and all smartphones on the market include at least one MIPI specification. MIPI specifications are used in hundreds of millions of smartphones.

MIPI Alliance specifications cover the full range of interface needs in a device. The specifications can be applied to integrate the modem, application processor, camera, display, audio, storage, antennas, tuner, power amplifier, filter, switch, battery, sensors, and other components.

Component vendors and device manufacturers use MIPI Alliance specifications because the technologies simplify designs, reduce design costs and shorten time-to-market for efficient, high-performing products. And fundamentally, each specification is optimized to ensure three performance characteristics needed in a mobile device: low power to preserve battery life, high-bandwidth to enable feature-rich applications, and low electromagnetic interference (EMI) to optimize performance of radios and subsystems.

Tablets, laptops and hybrid devices

Devices that converge mobile and computing capabilities are important markets for MIPI Alliance specifications. MIPI specifications helped establish and advance the tablet market and many organizations in the PC industry use MIPI specifications in mobile-connected laptops, tablet/laptop hybrids and other devices. Typical use cases for MIPI specifications in these devices include connecting and managing power consumption for high-definition displays and minimizing the number of wires deployed through hinges to connect cameras or displays.


MIPI specifications address only the interface technology, such as signaling characteristics and protocols; they do not standardize entire application processors or peripherals. Products which utilize MIPI specs will retain many differentiating features. By enabling products which share common MIPI interfaces, system integration is likely to be less burdensome than in the past.[8]

MIPI is agnostic to air interface or wireless telecommunication standards. Because MIPI specifications address only the interface requirements of application processor and peripherals, MIPI compliant products are applicable to all network technologies, including GSM, CDMA2000, WCDMA, PHS, TD-SCDMA, and others.

Some of the specifications by MIPI include:

  • Camera Serial InterfaceDisplay Serial Interface
  • Display pixel interface
  • System Power Management Interface (SPMI)
  • SoundWire, introduced in 2014[12]

MIPI CSI Interface

CSI stands for Camera Serial Interface. It specifies high speed serial interface between a host processor and camera module. Figure-2 depicts MIPI CSI-2 Interface.

Following are the features of MIPI CSI-2 Interface.

  • It is high performance serial interface between image sensor and application processor.
  • It uses D-PHY physical layer with upto 4 data lines which provides data throughput of about 4Gbps.
  • Separate I2C compliant interface used for camera control functions as shown.
  • MIPI CSI interface offers following benefits.
  • Scalability • Lower power • improved reliability • lower system cost

MIPI DSI Interface

 DSI stands for Display Serial Interface. It is High speed and high performance serial interface. The DSI interface offers efficient, low power and low pin count connectivity between application processor and display module (or display bridge IC). It uses MIPI D-PHY as physical layer. Following are the features of MIPI D-PHY.

  • It uses 4 data lines with 1 common differential line
  • Throughput upto 1Gbps can be achieved.
  • Both pixel and data commands are serialized into single physical stream between processor and display IC. The status is conveyed from display IC to application processor.

MIPI Testing


You need to design mobile devices that address the evolving data storage, data transfer, display, camera, memory, power, and other requirements defined by MIPI specifications. Customers demand higher performance, real time streaming of multimedia content and feature-rich applications.


You need to test the performance of your MIPI transmitter device to ensure it is not the root cause of signal impurities at the receiving end of the transmission line. MIPI D-PHY, M-PHY and C-PHY all have unique transmitter test challenges. With hundreds of tests to be performed, you can save significant test time by using automated compliance test software.


You need to test your MIPI receiver device to ensure it can properly detect the digital signal content of an input signal. It is important to test it against a worst-case stress condition to account for signal degradation in the transmission channel. You need an accurate high-speed signal stimulus, as well as bit error detection capabilities, to test the performance of your MIPI receiver. Automated compliance test software enables you to quickly test all key parameters of your designs.


Protocol validation occurs predominately at the interface layer. There are many different protocols supported on the PHY layer of the MIPI specifications, including CSI-2, DSI-1, DigRF, CSI-3, UFS, UniPro, SSIC, and MPCIe. Each protocol has its own unique requirements and tests. For both MIPI D-PHY and M-PHY protocols, there is a stack between the physical and link layer, as well as between the transport and high-level application layer. To truly identify where an error exists, it is ideal to be able to “see into” that stack.

How MIPI Interfaces Enable 5G Smartphones

The first wave (phase 1) of high-end 5G smartphones is expected to be an enhancement of the high-end 4G devices currently on the market. Major enhancements will include the addition of the new 5G NR RF subsystem, and the evolution of other subsystems to enable better user experiences and richer multimedia capabilities. For example, these 5G smartphones may have three to four high-resolution rear cameras with high-frame-rate/slow-motion video capture capability, an enhanced microphone array, multi-channel audio and stereo speakers.

The 5G modem and application processor use MIPI specifications such as CSI-2 for cameras and DSI-2 for the display, as well as either the low-power, high-bandwidth, pin-efficient MIPI D-PHY or C-PHY physical layers. MIPI RFFE for RF front-end devices control, and MIPI UniPro with M-PHY for high-performance flash storage are all becoming ubiquitous in 5G designs. MIPI I3C, SoundWire, SLIMbus and upcoming VGI specifications are expected to be adopted in many upcoming 5G smartphone platforms as well.


MIPI CSI-2 is the most widely used camera interface in mobile and other markets. It has achieved widespread adoption for its ease of use and ability to support a broad range of high-performance applications, including 1080p, 4K, 8K and beyond video, and high-resolution photography.

Designers should feel comfortable using MIPI CSI-2 for any single- or multi-camera implementation in mobile devices. The interface can also be used to interconnect cameras in head-mounted virtual reality devices; automotive smart-car applications for infotainment, safety, or gesture-based controls; imaging applications for client content creation and consumption products; camera drones; IoT appliances; wearables; and 3D facial recognition security or surveillance systems.

The latest release, MIPI CSI-2 v3.0, delivers enhancements to the specification designed to enable greater capabilities for machine awareness across multiple application spaces, such as mobile, client, automotive, industrial IoT and medical. RAW-24, for representing individual image pixels with 24-bit precision, is intended to enable machines to make decisions from superior quality images; an autonomous vehicle, for example, could decipher whether darkness on an image is a harmless shadow or a pothole in the roadway to be avoided. Smart Region of Interest (SROI)—for analyzing images, inferencing algorithms and making better deductions—could enable machines on a factory floor, for example, to more quickly identify potential defects on a conveyor belt, or medical devices to more surely recognize anomalies such as tumors. And Unified Serial Link (USL)—for encapsulating connections between an image sensor module and application processor—is crucial for reducing the number of wires needed in IoT, automotive and client products for productivity and content creation, such as all-in-one and notebook platforms.

MIPI CSI-2 can be implemented on either of two physical layers from MIPI Alliance: MIPI C-PHY v2.0 or MIPI D-PHY v2.5. It is backward compatible with all previous MIPI CSI-2 specifications. Performance is lane-scalable, delivering, for example, up to 41.1 Gbps using a three-lane (nine-wire) MIPI C-PHY v2.0 interface, or 18 Gbps using four-lane (ten-wire) MIPI D-PHY v2.5 interface under MIPI CSI-2 v2.1.

Testing of MIPI-Specification-Based Devices

The latest trend for semiconductor device manufacturers is to add several high-speed MIPI® specification-based ports to a single device. This enables feature-rich implementations of imaging- and display-intensive applications, although it also poses significant challenges for production test engineers who are tasked with creating high-fault coverage testing solutions on automated test equipment (ATE). Such fault coverage often entails creating a parallel, at-speed, system-oriented functional test while simultaneously grappling with the limitations of legacy ATE and the complexity of the MIPI protocols being tested.

There are three high speed PHY-layer standards defined by MIPI, and they are used for different applications:

  • D-PHY is a variable speed unidirectional clock synchronous streaming interface, with low speed in-band reverse channel and supports interfaces for camera (CSI), and display (DSI).
  • M-PHY is performance driven, bidirectional packet/network oriented interface supporting interfaces like camera (CSI), storage (UFS), DigRF, and the UniPro, LLI, SSIC, M-PCIe which are used for inter-processor communications
  • C-PHY is a variable speed unidirectional, embedded clock streaming interface, with low speed in-band reverse channel and supports interfaces for camera (CSI), and display (DSI).

Each interface provides a wide range of parameters including clocking method, channel compensation, number of pins, maximum amplitude, data rate and format, bandwidth per port, data encoding, and clock recovery. The D-PHY, M-PHY, and C-PHY MIPI interfaces are not controlled by a compliance program because they are not accessible to users. However, validation of specification conformance is important to semiconductor vendors and system integrators to ensure interoperability between components.

The MIPI specifications and Conformance Test Suite (CTS) requirements for components are quite complex and testing them is challenging. Connectivity to the Device Under Test (DUT) while making sure signal integrity is maintained, creating the worst-case stimulus for the DUT while not overstressing it, or getting test result information from the DUT are examples of such challenges.

BER test solutions offer the flexibility to test all types of MIPI receivers accurately by providing accurate high speed signal stimulus and bit error detection capabilities. More complex C-PHY and D-PHY signal stimulation can be addressed with high performance arbitrary waveform generators. Automated test software helps to reduce test development and execution time while ensuring repeatability and accuracy.

Elevate competitive advantage in ATE

Elevate is a leading supplier of innovative, low power, high density components for the design of next generation Automated Test Equipment (ATE). With a proven track record of consistently delivering the highest density, lowest power solutions available, systems designed around Elevate products have a competitive advantage in the ATE market space and are able to adapt successfully to emerging trends and challenges while providing ever increasing end user value.

Elevate offers a wide variety of solutions for the ATE market with variable levels of integration so that we can serve the unique requirements of multiple end user segments such as System on a Chip (SOC) Test, Memory Test, Test During Burn-in (TDBI), In-Circuit Test (ICT) and beyond.

Elevate’s mission is to serve our semiconductor and system test customers by providing world class test integrated circuits (ICs) that address the industry’s most complex ATE challenges.  We strive to exceed our customer’s expectations, now and well into the future, through designing the lowest power/highest density solutions, with the goal of providing the lowest possible cost of test. 

Chip Mask

Elevate Intro


Technology aficionados know Moore’s Law which states the number of transistors in a dense integrated circuit doubles every two years. Few think about how those chips are designed, produced, and tested. As silicon content in electronics increase, functionality grows exponentially, requiring size, power, and cost to decrease. The need to test the chips for fabrication defects is essential to provide working components and ensure long life performance. The tests undertaken in production must be suitably comprehensive and at the lowest cost possible. Someone has to build the chips that test ALL these ICs – that company is ElevATE Semiconductor.

At ElevATE, we design and build integrated circuits which test all functions of a semiconductor from the key parametrics: power, speed, voltage, plus the overall system in which the chip is designed to operate. We can identify defects in processing and performance or variation across parameters over time. Our solutions provide all the data I/O, measure the parametrics, supply power, and the power response to the device under test (DUT). Our circuits are accurate enough to characterize the latest high-speed server processors, memory modules, and artificial intelligence (AI) FPGAs used in data center applications.

Ask any engineer and you will be told test engineers are a special breed. Our founders, and many of our team, have been in the semiconductor test space since the early 90’s. A spinout of Intersil in 2012, ElevATE’s heritage goes back to early 2000 as PlanetATE where many of our solutions were first architected. Our customers include the largest semiconductor test companies, startup test firms, test houses, and semiconductor manufacturers. They have procured products which were designed-in over 10 years ago and continue to ship on production boards today. We anticipate our new designs to be available at least that long going forward.

Our customer’s evolving challenges dictate our next generation of products. Semiconductor test continues its march toward lower test times, with more devices under test simultaneously with the goal of minimizing the costs of testing. We see more demand for the lowest power possible at even higher speeds and higher channel counts, which challenges our engineers to push the limits of process and design.

We focus on test and know importance of quality is for our design, manufacturing, and support processes. ElevATE is ISO9001 certified and a continuous improvement organization. Our products go through rigorous qualification thorough testing and characterization before finding their homes on customer boards – in fact, each chip can go through over 3,000 analog tests before being made ready for shipment.

We offer numerous ways to customize our products to meet the wide variety of our customer’s technical needs. If you have state of the art technology, you need the best test circuits in the world to test it – engage us and see why our experience, portfolio of world class products, and our team are the best in the industry!

SE-DPIN: Scalable (16 .. 256+) I/O card Technology for PXIe and Custom ATE instruments

Salland Engineering delivers over 28 years of services to develop and build custom ATE instruments for the semiconductor industry. CEO, Paul van Ulsen said; “Building high density instruments is always about finding the right balance between performance, density/throughput within the right available power & cooling at the right cost per channel.“

To address these challenges, Salland decided to design the Instrument IP themselves. This enables customers to benefit from proven & available building blocks to achieve high performance and very high density at the right cost.

Salland’s ‘’off-the-shelf’’ custom OEM instrument solutions allow customers to build  ATE instruments at a fraction of the cost and at minimal risk. In this respect Salland follows a similar approach as Elevate, building standard solutions for custom applications.

Salland’s latest proof of concept is a scalable 200MHz DPin IO technology based on ElevATE’s Mystery Octal SOC ASIC.  This is a 64ch PXIe card with 8 Mystery ICs onboard featuring:

  • 64 (/32)-channel, 200MHz/up to 500Meps Digital I/O card in PXIe format
  • Based on ElevATE Mystery ASIC and a FPGA based timing generator
  • Scalable architecture in blocks of 16 channels up to 256+
  • Technology can be used in all kind of form-factors; modules, ATE, PXIe, etc.

With the Mt. Mystery ASIC, Salland was able to dramatically increase channel count and speed in an air-cooled solution designed to fit into the strict power/space requirements for a PXIe card. 

Air Cooled

SE-DPIN: PXI I/O card Specifications

Form-factor Single slot, 3U PXI
# Channels 64 (or 32) independent I/O
Large Vector Memory 256M vectors
Scan Memory Up to 4G vectors (optional)
Error Memory 1k
Max vector rate 200MHz (39ps Res),  upto 500Meps
Max offset (DGS – GND) ±300mV
High Voltage Mode
Frequency range 100Hz…50MHz
Voltage range -2.0V to +6.0V
High Speed Mode High Speed mode Single ended/Differential LVDS
Frequency range 100Hz…200MHz
Voltage range 0.0V to +4.0V
block to IO card

CEO’s COVID-19 Update

Our focus has always been on making our customers successful, by providing the highest quality/highest density test ICs in the industry, as well as the best support. Given the evolving COVID-19 situation, many have asked about ELEVATE’s order fulfillment capabilities, so we wanted to give you an update such that that you may plan accordingly.

ELEVATE has long had a business continuity plan (BCP) in place to handle unforeseeable situations, such as the one we are experiencing with COVID-19. As such, ELEVATE has invested to minimize customer disruptions, holding more inventory than a large public company would, across our product portfolio.

These investments will minimize disruptions, but not completely eliminate them.  We have seen delays in certain areas of the supply chain, but we can assure you that we have product on hand, and on order (well before this situation occurred), to address many of these slowdowns.  New products such as Mystery and Whitney are being produced, tested and packaged now, and work continues on all products currently in development. 

Standard lead time for orders is 8 weeks, but expedited shipping inside of that period is available for a nominal charge.  We ask all customers who are able to provide a forward-looking, non-binding forecast which allows us to better plan our supply and notify you of any issues well in advance. 

The team at ELEVATE is working diligently to continue to support you during this unprecedented time.  If you have specific needs that are not addressed in this update, please contact us directly.  We will continue to keep you updated, as warranted, as the situation evolves.

Best Regards,

David J. Kenyon

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SOC Octal 500 MHz Integrated Pin Electronics/DAC/PPMU/Deskew

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