Powering the Next Generation of Semiconductor Test
At ElevATE, the test operations organization supports the product throughout the entire product life cycle, from product concept through end of life. This equates to a versatile team, that performs both project development work and operational sustaining work. The Senior Test Engineer candidate will be responsible for their assigned project from DFT, through development and volume production.
This starts at the concept phase where the TE candidate will be responsible to interface with the development team on design for test (DFT) and design for manufacturing (DFM) concepts and implementation. As the project enters the silicon development phase, the Test Engineer will be responsible to fully develop all aspects of the test application. This includes that ATE hardware and software.
During the silicon evaluation phase, the Test Engineer will work closely with the Product Engineer to develop a characterization program and to determine the performance of the device.
As the device enters production, the candidate is expected to work closely with the production facilities to transfer the application to the production site and to work any sustaining issues if they occur. Sustaining work includes test program and data log evaluations to optimize test times and yields, ports to different sites for capacity flexibility and cost reduction.
The candidate will be the primary technical test engineering interface to the development teams as well as the production facilities. Design for test methodologies and yield enhancement initiatives will be important success criteria for the role.
The devices developed by ElevATE are complex analog devices (large analog, small digital content). The job applicant is expected to be an expert in Analog test development
- Lead and continually develop the Test Engineering discipline including managing direct reports, standards and infrastructure, our internal test floor and equipment, and yield management systems and processes
- Design load boards, probe cards and test software to fully ATE test VLSI SOC devices which have both a large digital content as well as analog and high speed SerDes busses
- Develop high level test engineering strategies by product families, Develop test program for multi-site testing for final test (Package) and wafer level testing.
- Work with outside vendors for load boards and sockets development for new devices
- Requires strong understanding of Analog IC testing techniques
- Ability to run standard translation tools (Velocity, Test Insight or similar) for vector conversion from simulation files in VCD/EVCD and WGL formats
- Understanding of Scan, at-speed scan, JTAG, Memory BIST, OTP memory programming and loopback techniques.
- Develop ATE characterization program for critical data sheet parameters.
- Work with designers to think outside the box to develop complex test methodologies for device capabilities that exceed the current tester capabilities
- Expert in large scale ATE platforms like Teradyne Ultraflex (preferred), and/or Verigy Pinscale /Smartscale
- Bring up and support of test program at overseas vendors, support production for any ATE related issues
- Support Product Engineer, FA and QA team for production qualification and customer issues
Work with team members and venders, define ATE Test Specification and drive test review
- Support early-stage ES (Engineering Sampling) and CS (Customer Sampling) activities if needed
- Coordinate with Product Engineers and Quality Assurance on Yield Management Systems and use cases so to have an enterprise-wide platform for yield improvement and institutional product knowledge.
- Support and manage Sustaining Engineer on ElevATE strategic plans for test platform transitions and site to site ports and qualification.
- Responsible for developing strategic plan for maturing the local test environment, and educating junior employees on best-in-class approaches
- Actively enhance the network of suppliers, contractors so to supporting insource vs outsource workloads and future roadmap needs
- Responsibility for process documentation of critical activities, and be the point of contact for ISO, customer audits
- Minimum Requirement of B.S.E.E. with 8+ years’ of direct Test Engineering experience
- Strong experience in complex Analog test development
- Mixed signal background for ADC, DAC, PLL
- Programming experience in C, C++, VBT, Linux, Unix environments
- General knowledges on Test Correlation, GRR and NPI Flow
- Capable of taking products from first silicon to final production with minimal supervision
- Test Program Version Control in SVN Repository or GIT
- Familiarity with Scripting languages like PERL, AWK to parse data logs and formatting